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Class Information
- Lectures:
- Section A00: MW 2:00p-3:20p, EBU1-2315
- Section B00: MW 3:30p-4:50p, EBU1-2315
- Discussion: No discussion sections
Instructor
Teaching Assistants
TA Office Hours
- Mon 11-2 (Ping Yin)
- Tue 11-2 (Yuqi Huang)
- Thu 11-2 (Dylan Vizcarra)
- Fri 11-2 (Jianling Liu)
- Fri 2-5 (Justin Law)
- All TA office hours will be held in EBU1-5101 (cubicle D)
Recommended (Not Required) Textbook
- Digital Design and Computer Architecture, Second Edition
David Harris and Sarah Harris (Authors)
Morgan Kaufmann; ISBN-10: 0123944244; ISBN-13: 978-0123944245
- We will only be using Chapter 4 of this book,
which provides a good overview of SystemVerilog with good examples.
- Make sure you get the 2nd Edition since the 1st Edition uses Verilog instead of SystemVerilog.
- Book recommended, but not required.
Piazza for Announcements
- 02-13:
Here are the results for Project 3:
- Best Delay: #ALUTs = 1349, #Registers = 1129, Area = 2478, Fmax = 187.51 MHz, #Cycles = 144, Delay (microsecs) = 0.768, Area*Delay (millesec*area) = 1.903
- Best Area*Delay: #ALUTs = 1197, #Registers = 1147, Area = 2344, Fmax = 187.67 MHz, #Cycles = 150, Delay (microsecs) = 0.799, Area*Delay (millesec*area) = 1.874
- Median Result: #ALUTs = 1458, #Registers = 1129, Area = 2587, Fmax = 110.82 MHz, #Cycles = 174, Delay (microsecs) = 1.570, Area*Delay (millesec*area) = 4.062
- 01-07:
If you have not already enrolled yourself on the class Piazza site, please enroll right away
here.
We will be doing all of our announcements on Piazza this quarter, so please make sure that you sign up as soon as possible.
Software for this Course
-
In this class, we will be using the SystemVerilog hardware description language for our design projects.
To get started, please go to the software download page
for instructions on how to download the Quartus Prime Lite Edition software suite (version 18.1),
which includes the Quartus Prime Verilog/SystemVerilog compiler and the ModelSim-Altera FPGA Edition logic simulator.
Earlier versions of Quartus Prime before Intel acquired Altera were called Quartus II.
-
Before the second week of class, you should have the following accomplished:
-
The specific FPGA device that we will use for this class is
- Device family: Arria II GX
- Device name: EP2AGX45DF29I5
This device is the last device in the select menu for the Arria II GX family.
We will use this device for reporting area and delay performance.
- The Windows machines in EBU1-4309 have also been setup with the Quartus Prime Lite
and ModelSim software if you are unable to get the software to work on your own laptop/machine.
If you are enrolled in the class, you should be able to get the door code from
here.