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Class Information
- Lectures:
- Section A00: Tu Th 9:30am-10:50am, MANDE B-210
- Section B00: Tu Th 11:00am-12:20pm, CENTER 216
- Discussion: No discussion sections
Instructor
Teaching Assistants
- Qingzi Lan
Email: lanqingzi@gmail.com
Office hours: Mon 3:30-6:30pm, Wed 4:30-7:30pm, EBU1-5101 (cubicle D)
- Kevin Luong
Email: kqluong@ucsd.edu
Office hours: Thu 3-6pm, Fri 3-6pm, EBU1-5101 (cubicle D)
- Ping Yin
Email: piyin@eng.ucsd.edu
Office hours: Tue 4-6pm EBU1-5101 (cubicle D)
Recommended Textbook
- Digital Design and Computer Architecture, Second Edition
David Harris and Sarah Harris (Authors)
Morgan Kaufmann; ISBN-10: 0123944244; ISBN-13: 978-0123944245
- We will only be using Chapter 4 of this book,
which provides a good overview of SystemVerilog with good examples.
- Make sure you get the 2nd Edition since the 1st Edition uses Verilog instead of SystemVerilog.
- Book recommended, but not required.
Announcements
- 06-15:
For the final project, the median results are:
- Median Delay: 20.917 microsec
- Median Area*Delay: 106.053 millisec*area
The top designs for Best Delay are:
- Justin Law and Kevin Hang:
- #ALUTs = 4375, #Registers = 1222, Area = 5597
- Fmax = 134.16 MHz, #Cycles = 1691
- Delay = 12.604 microsec, Area*Delay = 70.547 millsec*area
- Zhe Zhang and Aadil Ahmed:
- #ALUTs = 7765, #Registers = 1415, Area = 9180
- Fmax = 138.33 MHz, #Cycles = 1766
- Delay = 12.767 microsec, Area*Delay = 117.197 millsec*area
- Nikhil Nair and Niral Pathak:
- #ALUTs = 4075, #Registers = 1322, Area = 5397
- Fmax = 133.71 MHz, #Cycles = 1739
- Delay = 13.006 microsec, Area*Delay = 70.192 millsec*area
The top designs for Best Area*Delay are:
- Christopher Cabreros and Dan Zhu:
- #ALUTs = 2258, #Registers = 1274, Area = 3532
- Fmax = 145.31 MHz, #Cycles = 1961
- Delay = 13.495 microsec, Area*Delay = 47.665 millsec*area
- Oleksandr Korshak and Dan Volkovich:
- #ALUTs = 1920, #Registers = 1194, Area = 3114
- Fmax = 116.47 MHz, #Cycles = 1955
- Delay = 16.785 microsec, Area*Delay = 52.270 millsec*area
- Divyata Sharma and Kelly Robertson:
- #ALUTs = 2110, #Registers = 1143, Area = 3253
- Fmax = 119.23 MHz, #Cycles = 1965
- Delay = 16.481 microsec, Area*Delay = 53.612 millsec*area
Congratulations!!!
Please email Prof. Lin if we missed your partner's name or if you think your design should be in the top 3, but is not listed.
- 05-09:
Project 4 due date extended to Thursday 5/11. Project 5 due date changed to Thursday 5/25.
- 05-08:
For the final project testbench
tb_final_shp.sv,
the message size is 505 bytes.
Here is the Excel spreadsheet
FinalProject.xlsx of the intermediate values for this testbench.
The intermediate values are for
W[t],
A[t+1],
B[t+1],
C[t+1],
D[t+1], and
E[t+1]
for each time step "t".
Note that the values shown for time "t" for A ... E are the new values that they will become at time "t+1".
- 05-08:
For the Project 5 testbenches
tb_md5.sv
and tb_sha256.sv,
the message size is 120 bytes.
Here is the Excel spreadsheet
Project5.xlsx of the intermediate values for both testbenches.
The intermediate values are for
W[t],
A[t+1],
B[t+1],
C[t+1],
D[t+1], and
E[t+1]
for each time step "t".
Note that the values shown for time "t" for A ... E are the new values that they will become at time "t+1".
- 05-08:
For Project 4, the only requirement is a working synthesizable design. A good design will have the following results:
- #ALUTs = 781, #Registers = 924, Area = 1705
- Fmax = 197.86 MHz, #Cycles = 295
It is fine if your Project 4 results are not as good as this. The top teams in the past have gotten better results than this, but this is a reasonable target. The only requirement for Project 5 is also working synthesizable design. However, for the final project, we will be posting minimum passing requirements.
- 05-08:
For the Project 4 testbenches
tb_sha1.sv
and tb_sha1_511.sv,
the message sizes are 120 bytes and 511 bytes, respectively.
Here is the Excel spreadsheet
Project4.xlsx of the intermediate values for both testbenches.
The intermediate values are for
W[t],
A[t+1],
B[t+1],
C[t+1],
D[t+1], and
E[t+1]
for each time step "t".
Note that the values shown for time "t" for A ... E are the new values that they will become at time "t+1".
- 04-07:
A Piazza page has been set up. You can enroll yourself
here.
- 04-04:
For Mac users, you can use BootCamp
to dual boot Windows.
- 04-04:
Apparently, JSOE students have access to free Microsoft software, including Windows 10.
See here.
- 04-04: Welcome to the first day of class.
In this class, we will be using the SystemVerilog hardware description language for our design projects.
To get started, please go to the software download page
for instructions on how to download the Quartus Prime Lite Edition software suite (version 16.1),
which includes the Quartus Prime Verilog/SystemVerilog compilter and the ModelSim-Altera FPGA Edition logic simulator.
Earlier versions of Quartus Prime before Intel acquired Altera were called Quartus II.
- 04-04: Please use the following FPGA for all your projects:
- Device family: Arria II GX
- Device name: EP2AGX45DF29I5
This device is the last device in the select menu for the Arria II GX family.
This is the largest FPGA device in this family.
We will use this device for reporting area and delay performance.
- 04-04: Before next Tuesday 04-14, you should have the following accomplished: