Menu:

• Home
• Class Schedule
• Software Downloads
• Projects

Class Information

• Lectures:
  • Section A00: MW 2:00p-3:20p, EBU1-2315
    
  • Section B00: MW 3:30p-4:50p, EBU1-2315
    
• Discussion: No discussion sections

Instructor

• Prof. Bill Lin, Atkinson Hall 4310
• Office hours: Mon 1:00-1:50p
• Email: billlin@eng.ucsd.edu

Teaching Assistants

• Jianling Liu (jil096@ucsd.edu)
• Justin Law (jklaw@ucsd.edu)
• Dylan Vizcarra (dvizcarr@ucsd.edu)
• Yu Huang (yqhuang@ucsd.edu)
• Ping Yin (piyin@eng.ucsd.edu)

TA Office Hours

• Mon 11-2 (Ping Yin)
• Tue 11-2 (Yuqi Huang)
• Thu 11-2 (Dylan Vizcarra)
• Fri 11-2 (Jianling Liu)
• Fri 2-5 (Justin Law)
• All TA office hours will be held in EBU1-5101 (cubicle D)

Recommended (Not Required) Textbook

• Digital Design and Computer Architecture, Second Edition
  David Harris and Sarah Harris (Authors)
  Morgan Kaufmann; ISBN-10: 0123944244; ISBN-13: 978-0123944245
• We will only be using Chapter 4 of this book, which provides a good overview of SystemVerilog with good examples.
• Make sure you get the 2nd Edition since the 1st Edition uses Verilog instead of SystemVerilog.
• Book recommended, but not required.

Piazza for Announcements

• 03-29: Final project results.
  MEDIAN RESULTS:
  • Delay (us) = 1.647 for DELAY-OPTIMIZED DESIGNS
  • Area*Delay (ms*area) = 45.280 for AREA*DELAY-OPTIMIZED DESIGNS
  
  TOP 3 DELAY-OPTIMIZED DESIGNS:
  1. Mingbin, Li and Jorge Alexandro Avila
     #ALUTs = 26788, #Regs = 22564, Area = 49352, Fmax = 184.26 MHz, #Cycles = 223, Delay (us) = 1.210, Area*Delay (ms*area) = 59.728
  2. Michael Wibowo
     #ALUTs = 18821, #Regs = 17012, Area = 35833, Fmax = 179.44 MHz, #Cycles = 218, Delay (us) = 1.215, Area*Delay (ms*area) = 43.533
  3. Thiago Goncalves Marback and David Li
     #ALUTs = 21030, #Regs = 20580, Area = 41610, Fmax = 172.47 MHz, #Cycles = 220, Delay (us) = 1.276, Area*Delay (ms*area) = 53.077
  TOP 3 AREA*DELAY-OPTIMIZED DESIGNS:
  1. Thiago Goncalves Marback and David Li
     #ALUTs = 2057, #Regs = 2446, Area = 4503, Fmax = 207.64 MHz, #Cycles = 1164, Delay (us) = 5.606, Area*Delay (ms*area) = 25.243
  2. Team wanted to remain anonymous
     #ALUTs = 1217, #Regs = 1132, Area = 2349, Fmax = 193.95 MHz, #Cycles = 2200, Delay (us) = 11.343, Area*Delay (ms*area) = 26.645
  3. Michael Wibowo
     #ALUTs = 1334, #Regs = 1208, Area = 2542, Fmax = 193.72 MHz, #Cycles = 2201, Delay (us) = 11.362, Area*Delay (ms*area) = 28.882
  Congratulations!!!

• 03-07: Here are the results for Project 4:
  • Best Delay: #ALUTs = 26616, #Registers = 16990, Area = 43606, Fmax = 107.69 MHz, #Cycles = 453, Delay (microsecs) = 4.207, Area*Delay (millesec*area) = 183.429
  • Best Area*Delay: #ALUTs = 1334, #Registers = 1208, Area = 2542, Fmax = 193.72 MHz, #Cycles = 2201, Delay (microsecs) = 11.362, Area*Delay (millesec*area) = 28.882
  • Median Result: #ALUTs = 1898, #Registers = 1664, Area = 3562, Fmax = 106.45 MHz, #Cycles = 2435, Delay (microsecs) = 22.875, Area*Delay (millesec*area) = 81.479
  The Best Delay design submitted for project 4 is due to a parallel design. Otherwise, the Best Area*Delay design submitted for project 4 is also the Best Delay non-parallel design.

• 02-13: Here are the results for Project 3:
  • Best Delay: #ALUTs = 1349, #Registers = 1129, Area = 2478, Fmax = 187.51 MHz, #Cycles = 144, Delay (microsecs) = 0.768, Area*Delay (millesec*area) = 1.903
  • Best Area*Delay: #ALUTs = 1197, #Registers = 1147, Area = 2344, Fmax = 187.67 MHz, #Cycles = 150, Delay (microsecs) = 0.799, Area*Delay (millesec*area) = 1.874
  • Median Result: #ALUTs = 1458, #Registers = 1129, Area = 2587, Fmax = 110.82 MHz, #Cycles = 174, Delay (microsecs) = 1.570, Area*Delay (millesec*area) = 4.062

• 01-07: If you have not already enrolled yourself on the class Piazza site, please enroll right away here. We will be doing all of our announcements on Piazza this quarter, so please make sure that you sign up as soon as possible.

Software for this Course

• In this class, we will be using the SystemVerilog hardware description language for our design projects. To get started, please go to the software download page for instructions on how to download the Quartus Prime Lite Edition software suite (version 18.1), which includes the Quartus Prime Verilog/SystemVerilog compiler and the ModelSim-Altera FPGA Edition logic simulator. Earlier versions of Quartus Prime before Intel acquired Altera were called Quartus II.

• Before the second week of class, you should have the following accomplished:
  • Install the Quartus/Modelsim software suite.
  • Go through our Quartus and ModelSim tutorial pages.

• The specific FPGA device that we will use for this class is
  • Device family: Arria II GX
  • Device name: EP2AGX45DF29I5
  This device is the last device in the select menu for the Arria II GX family. We will use this device for reporting area and delay performance.

• The Windows machines in EBU1-4309 have also been setup with the Quartus Prime Lite and ModelSim software if you are unable to get the software to work on your own laptop/machine. If you are enrolled in the class, you should be able to get the door code from here.