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Schedule (subject to change)

Week Date Topic Materials
1 01/07 Lecture 1 (pptx, pdf)
Class Introduction and SystemVerilog
Here is a Quartus/ModelSim tutorial.

Here are the SystemVerilog code and testbench files used in this tutorial: fibonacci_calculator.sv, tb_fibonacci_calculator.sv.
01/09 Lecture 2 (pptx, pdf)
SystemVerilog
Examples: fulladder.sv, h4ba.sv, add4.sv, ex1.sv, ex2.sv, ex3.sv, p4ba.sv, sevenseg.sv, priority_casez.sv, add_sub.sv.
2 01/14 Lecture 3 (pptx, pdf)
SystemVerilog
Examples: ex4.sv, ex5.sv, ex6.sv, ex7.sv, ex8.sv. ex9.sv, ex10.sv, divideby3FSM.sv, fsm2.sv.
01/16 Lecture 4 (pptx, pdf)
FSMs, Fibonacci, Project 1
RTL Example: rtl_example.sv.
3 01/21 Martin Luther King, Jr. Holiday
01/23 Lecture 5 (pptx, pdf)
Project 2
Complete Project 1 before class (but no need to submit anything as this project not graded)

Sample Project 1 implementation of 2-state Fibonacci calculator: fibo2state.sv.

Here are 2 other implementations, one with no state, other with combinational logic: fibo0state.sv, fibo_combo.sv.
4 01/28 Lecture 6 (pptx, pdf)
SHA-256.
Complete Project 2 before class (but no need to submit anything as this project not graded)

Sample Project 2 implementations: byte_rotation.sv, br1.sv, br2.sv, br3.sv.

Here is the testbench for Project 3: tb_simplified_sha256.sv

Here are the SHA256 intermediate values: simplified_sha256.xlsx

Here are the wt values at time t: simplified_sha256_w_values.xlsx
01/30 Lecture 7 (pptx, pdf)
More on SHA-256
5 02/04 Lecture 8 (pdf)
More SystemVerilog Features
Running ModelSim in command line mode: modelsim_cmd.html

Paper on SystemVerilog features: 2013-SNUG.pdf
02/06 Lecture 9 (pptx, pdf)
FPGAs vs. ASICs
6 02/11 Lecture 10 (pptx, pdf)
Bitcoin hashing and Projects 4 and 5
Project 3 due Mon 2/11 before 11:59 pm

Here is the testbench for Projects 4 and 5: tb_bitcoin_hash.sv.

Here is a spreadsheet of intermediate values for the testbench: bitcoin_hash.xlsx

Here are the wt values at time t for all 3 phases for all nonces: bitcoin_hash_w_values.xlsx
02/13 Design Review Meetings

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7 02/18 Presidents' Day Holiday
02/20 Design Review Meetings

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8 02/25 Design Review Meetings

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Project 4 due Mon 2/25 before 11:59 pm
02/27 Design Review Meetings

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9 03/04 Lecture 11 (pptx, pdf)
Final Project Submission and More Tips
03/06 Additional Design Review Meetings

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Note: 3:30-6:30pm in EBU1-5101 (not 2-5 pm in EBU1-2315)
10 03/11 Additional Design Review Meetings

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Note: 3:30-6:30pm in EBU1-5101 (not 2-5 pm in EBU1-2315)
03/13 Lecture 12 (pptx, pdf)
VHDL and Testbenches
03/14 Additional Design Review Meetings

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Note: 3:30-6:30pm in EBU1-5101 (not 2-5 pm in EBU1-2315)
11 03/20 Final Project due date extended to Wed 3/20 before 11:59 pm

Use this template Final-Report-Template.docx for your final report.

Summarize your final results using this spreadsheet finalsummary.xlsx

Submit them with the rest of your files.